The Intel Optimization Reference, under Section 3.5.1, advises:
"Favor single-micro-operation instructions."
"Avoid using complex instructions (for example, enter, leave, or loop) that have more than 4 micro-ops and require multiple cycles to decode. Use sequences of simple instructions instead."
Although Intel themselves tell compiler writers to use instructions which decode to few micro-ops, I can't find anything in any of their manuals which explains just how many micro-ops each ASM instruction decodes to! Is this information available anywhere? (Of course, I expect that the answers will be different for different generations of CPUs.)
Answer
Agner Fog's PDF document on x86 instructions (linked off of the main page Hans cites) is the only reference I've found on instruction timings and micro-ops. I've never seen an Intel document on micro-op breakdown.
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